The present invention relates generally to a three-dimensional interconnect system for electrically interconnecting a plurality of electronic devices that are disposed on different physical planes. More specifically, the present invention relates to a three-dimensional interconnect system that includes a plurality of contiguously interconnected electrically conductive droplets that form an interconnect. The interconnect electrically connects electronic devices that are disposed on different physical planes.
Articles and publications set forth herein are presented for the information contained therein: none of the information is admitted to be statutory xe2x80x9cprior artxe2x80x9d and we reserve the right to establish prior inventorship with respect to any such information.
Modern electronic systems typically include a printed circuit board (PC board) or some other substrate upon which are mounted one or more integrated circuits (IC""s). Generally, the IC""s are electrically connected to the PC board by solder, for example. The solder is operative to electrically communicate the. IC""s with conductive traces on the PC board and to physically attach the IC""s to the PC board. In some applications the IC""s may also be attached to the PC board by an adhesive. As the physical geometries of semiconductor elements contained in an IC continue to shrink, it is possible to integrate several electronic functions onto a single IC. Resulting is an increase in the number of input and output connections (IO""s) that are required to communicate electrical signals to and from the IC.
One approach to increasing the number of available connections between an IC die and electronics external to the die is to connect the die to a PC board using solder balls. Typically, the IC die includes an array of bonding pads disposed on a surface of the IC die. The bonding pads are spaced apart by a predetermined pitch that matches the pitch of corresponding contact pads on the PC board or substrate. For example, the above mentioned approach is used in a flip-chip on PC board process to mount one or more IC die to a PC board. The solder bumps are operative to electrically connect the IC with conductive traces. Typically, a network of conductive traces and conductive vias disposed on the PC board are operative to electrically connect the IC to the other components.
FIG. 1 is an illustration of a prior art flip-chip assembly 1. The assembly 1 includes a substrate 3 and a semiconductor die 5. The substrate 3 includes contact pads 7 disposed on a surface of the substrate 3. For instance, the substrate 3 can be a PC board or a ceramic material used for multi-chip modules. The semiconductor die 5 includes bonding pads 9 disposed on a surface of the die 5. The die 5 and the substrate 3 are physically and electrically connected by solder balls 11 that are operative to electrically communicate the bonding pads 9 with the contact pads 7.
FIG. 2 is an illustration of another type of prior art flip-chip assembly 21. The assembly 21 includes a substrate 23 and a semiconductor die 25. The substrate 23 includes contact pads pads 27 disposed on a surface of the substrate 23. The semiconductor die 25 includes bonding pads 29 disposed on a surface of the die 25. The semiconductor die 25 includes columns 33 disposed on the bonding pads 29. The columns 33 are formed by depositing a conductive material on the bonding pads 29 to form the columns 33. A dielectric 35 is deposited on the semiconductor die 5 and surrounds the columns 33 thereby electrically insulating the columns 3 from one another. A portion of the dielectric 35 is removed so that the solder balls 31 can be deposited on the columns 33. The die 25 and the substrate 23 are physically and electrically connected by the solder balls 31 that are operative to electrically connect the bonding pads 29 with the contact pads 27.
FIG. 3 is an illustration of a prior art chip-scale assembly 41. The assembly 41 includes a substrate 43 and a semiconductor die 45. The substrate 43 includes contact pads pads 47 disposed on a surface of the substrate 43 and the semiconductor die 45 includes bonding pads 49 disposed on a surface of the die 45. The die 45 and the substrate 43 are physically and electrically connected by solder balls 51 that are operative to electrically communicate the bonding pads 49 with the contact pads 47. The bonding pads 49 are electrically connected to the solder balls 51 by vertical segments 63 and 67, and horizontal segments 75 and 77. In a manner similar to that shown in FIG. 2, dielectric layers 53, 55, and 57 are deposited on the die 5 to insulate the segments from one another. The solder balls, the vertical segments, and the horizontal segments of FIGS. 1 through 3 can be deposited using solder deposition techniques such as a demand mode solder jet droplet system. Other prior art methods for depositing solder balls include: physically placing prefabricated solder balls on the bonding pads; vapor phase deposition on a shadow mask to deposit solder on the bonding pads followed by reflowing the solder to form solder balls; and screen printing solder paste onto the bonding pads.
Due to the small size of an IC die and the large number of IO""s required for complex IC""s, the bonding pads and their corresponding contact pads as discussed above in reference to prior art FIGS. 1 through 3 can have a width in the range of about 50 xcexcm to about 100 xcexcm, and the pitch between pads can be in the range of about 100 xcexcm to about 250 xcexcm. As the number of IO""s continues to increase the pad width and the pitch will decrease to accommodate additional bonding pads.
There are several disadvantages to the Prior art assemblies of FIGS. 1 through 3. First, the solder bumping process used can include sputtering, vapor deposition, photolithography, photoresist, reflowing, and etching steps. Those steps are complicated, time consuming, and expensive. Moreover, those steps are susceptible to micro contamination and other yield reducing defects.
Second, to reduce the surface tension of the solder so that the solder will bond to the contact pad, a wetting metal such as nickel (Ni) is deposited on the contact pad using vacuum sputtering. After the sputtering step, another sputtering step is used to deposit a thin film of an anti-oxidation metal such as gold (Au) on the nickel to protect the nickel from being oxidized. Depending on the size of the PC board, the amount of gold required can be very expensive.
Third, the cost, complexity, and number of steps required in PC board manufacturing result in economies of scale that can only be realized over large production runs. Consequently, small production runs, custom production runs, and one-of-a-kind production runs are economically unpractical with current PC board manufacturing processes. For example, due to the small xcexcm spacings between bonding pads, the process for depositing the dielectric layers shown in FIGS. 2 and 3 requires precise manufacturing steps that are neither amendable to nor economically feasible for small production runs.
Fourth, CAD tools are used to lay out the pattern of conductive traces and vias on the PC board. Once the layout pattern is frozen and production of the PC board has begun, any design changes or errors in the layout can be costly and time consuming to implement. For example, in FIG. 3, a change in the layout positions of the contact pads 49 would require a new layout for the layers 53, 55, and 57, as well as a new layout for the vertical segments 63 and 67, and the horizontal segments 75 and 77.
Finally, the assemblies of FIGS. 1 through 3 do not allow for a direct connection between components disposed on a different physical planes. Instead, the substrate/PC board serves as an intermediate conductor between components to be connected. For example, when the components are mounted on opposing sides of a PC board, the conductive traces and vias of the PC board are operative to electrically communicate a component mounted on one side of the PC board with a component mounted on the opposite side of the PC board. On the other hand, even if components are mounted on the same side of the PC board a connection between the components is accomplished by the traces and vias. Since the PC board is fabricated prior to mounting the components, defects in the traces or vias can result in short circuits or open circuits that are difficult if not impossible to repair or rework.
Therefore, there is a need for an interconnect system that connects electronic devices that are disposed on different physical planes without using a PC board or the like, reduces the cost and complexity associated with PC board manufacturing, makes a direct connection between components, and can be used for to both large and small production runs.
The present invention provides a three-dimensional interconnect system that is operative to electrically connect electrical devices that are disposed on different physical planes. The present invention further provides a method for making a three-dimensional interconnect system in which conductive droplets are deposited to form an electrical connection between electrical devices that are disposed on different physical planes. Additionally, the present invention provides a system for making a three-dimensional interconnect system that includes a droplet ejector for ejecting the conductive droplets.
According to the system and method disclosed herein, at least two electronic devices can be electrically connected by an interconnect. The interconnect of the present invention can reduce the expense, complexity, time, and the number of steps required in conventional PC board, flip-chip, and multichip module (MCM) manufacturing processes. Additionally, interconnect of the present invention provides the advantage of reduced signal propagation delays by making a short and direct connection between electrical devices. Moreover, the method disclosed herein can be used for both small and large scale production runs. Furthermore, the method of the present invention provides the advantage of quick and low cost post-layout design changes. For example, a CAD program used for designing the layout pattern can be edited to change the layout.
In one embodiment of the present invention, a three-dimensional interconnect system includes a first electrical device disposed on a first physical plane and a second electrical device disposed on a second physical plane. An interconnect is disposed on a portion of the first and second electrical devices and the interconnect electrically connects the first electrical device with the second electrical device. The interconnect includes a plurality of contiguously interconnected electrically conductive droplets. Each droplet is in physical and electrical contact with an adjacent droplet so that the droplets form a single interconnect that can be disposed in three-dimensions. In essence, the droplets form a linked chain (a connecting line without any gap) that bridges a physical gap between the first and second electrical devices.
In a method according to the present invention, the three-dimensional interconnect system is formed by repeatedly ejecting successively contiguous electrically conductive drops along a path between first and second electrical devices to form an interconnect that bridges a physical gap between the first and second electrical devices, the interconnect is operative to electrically connect the first and second devices.
In a system according to the present invention, an ejector is used to eject electrically conductive droplets. The droplets impact a workpiece to form a contiguous interconnect. The interconnect is operative to electrically connect electrical devices that are disposed on the workpiece.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.